FREMO Interlocking
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IO boards for panels


The following two boards are under test. They have in common that they are ment to be used for a prototypical panel and can connect to train number displays via SPI.


This board is designed to be fixed under a single prototype SpDrS60 panel module. It is capable of driving 12V or 24V light bulbs and sample buttons that are connected to 12V or 24V.

A second generation of this board is manufactured. Boards are currently in use for "Stefanswiesen" and intended for "Delthin". The design works more or less. Software update with all 13 boards on the net does not work and sometimes a single board does not boot on power up of the system. There is a default pin usage for SpDrS60. List of connectors:

  • J1, PLUS, I1: one input and seven outputs for direct wiring to the bulbs and button in the local prototype field
  • J2: six pins for flat cable to neighboring field with up to one button and four bulbs
  • J3: three single outputs and two single inputs. There is a +12V pad for each of them. They are intended to connect single buttons or bulbs in neighboring fields or additional bulbs in the local field. A turnout needs 7+3=10 bulbs.
  • ISP_ZN: Connect programmer for In Circuit Programming or debugger for "debug Wire". Alternatively the SPI bus can be used to connect train number displays based on MAX7219. Wenn used for train number display, four bulb outputs can not be used.
  • LN: Power supply and TTL level LocoNet, "LoTUSNet".

IO board with 60 TTL level lines

This board is designed to interface with transistor based panel electronics for the Michelstadt

The first board and a second batch of three boards are currently in use. The operation in Rastede 2008 was promising but showed erratic behaviour. A debouncing algorithm is needed to avoid a message shower. But the message shower is probably triggered by bad electric design in the system or the board. More debugging will be done.


Both boards will use the same software. A configuration option decides over the pin usage which is both hardware dependant and about the decision wether to use the SPI processor pins for connection to a chain of train number displays or digital IO.

For digital IO, the software uses a test mode protocol that is used by Uhlenbrock to test their own panel boards. This protocol is based on the LNCV programming.

For access to the train number displays, the defined message based on OPC_PEER_XFER as defined by Digitrax.

For configuration the SV programming protocol is used. See this table of SVs.

Software update over LocoNet is available with the IPL protocol using a BootLoader.

LocoNet message bit to connector pad assignment

There is a little Java application that helps testing the IO functionallity of the boards.

Mode Configuration

SpDrS60 Michelstadt
Mode with ZN 1 5
Mode without ZN 0 4


LN Msg Bit
SpDrS60 Michelstadt
1. proto 2. proto   IC1     IC2     IC3     ZN  
0 OUT11 OUT11 A1 A11 A21  
1 OUT12 OUT12 C1 C11 C21  
2 OUT13 OUT13 A2 A12 A22  
3 OUT14 OUT14 C2 C12 C22  
4 OUT15 OUT15 A3 A13 A23 LOAD
5 OUT16 OUT16 C3 C13 C23  
6 OUT17 OUT17 A4 A14 A24  
7 OUT21 OUT23 n/a n/a n/a  
8 OUT22 OUT24 n/a n/a n/a  
9 OUT23 OUT25 n/a n/a n/a  
10 OUT24 OUT26 n/a n/a n/a  
11 OUT25 OUT31 n/a n/a n/a  
12 OUT26 OUT35 n/a n/a n/a  
13 OUT27 OUT39 n/a n/a n/a  
14 n/a n/a n/a n/a n/a  
15 n/a n/a n/a n/a n/a  
The cells that are marked orange are not used for IO if train number display (ZN) is enabled.

The cells that are marked blue are used by the bootloader to signal progress of a software update. Use this for direkt display. (For Michelstadt this could be a red LED for occupancy display.


LN Msg Bit
SpDrS60 Michelstadt
1. proto 2. proto   IC1     IC2     IC3   ZN
0 IN1 IN1 n/a n/a n/a  
1 IN2 IN22 n/a n/a n/a  
2 n/a IN33 n/a n/a n/a  
3 n/a IN37 C4 C14 C24 CLK
4 n/a n/a A5 A15 A25 DATA
5 n/a n/a C5 C15 C25 not usable
6 n/a n/a A6 A16 A26  
7 n/a n/a C6 C16 C26  
8 n/a n/a A7 A17 A27  
9 n/a n/a C7 C17 C27  
10 n/a n/a A8 A18 A28  
11 n/a n/a C8 C18 C28  
12 n/a n/a A9 A19 A29  
13 n/a n/a C9 C19 C29  
14 n/a n/a A10 A20 A30  
15 n/a n/a C10 C20 C30  
The cells that are marked orange are not used for IO if train number display (ZN) is enabled.

The cells that ar marked green are connected to the reset input of the processor. After completion of the design, it was choosen not to use this pin as IO. A connection to ground resets the device.